There exist of myriad of applications where a CMOS circuit requires precise phase shifted clock outputs, for example, when one signal must be guaranteed to arrive by an exact amount of time before (or after) another signal.
The typical method of achieving a predetermined delay at CMOS levels is to utilize CMOS buffers to create a predetermined delay. However, the disadvantage of this method is that the precision of the delay is very inaccurate. For example, to achieve a two nanosecond delay, the precision may at best be +/-500 picoseconds. This lack of precision is primarily due to CMOS transistor sensitivity to process, temperature and voltage variations.
Another attempt at generating precise multi-phase clock outputs has been implemented by Gazelle (now part of TriQuint Semiconductor) on part number GA1110. A technique is disclosed for achieving precise phase shifted output wherein the minimum delay is equal to the period of a clock signal. This clock signal is created by multiplying up a relatively low frequency signal to a high frequency internal signal via a phase-locked loop. The phase shifted outputs are provided by clocking a string of serially-coupled D-flip flops. Each D-flip flop inserts one period shift (or delay) in relation to the previous flip flop. Thus, the higher the frequency of the internal clock signal, the smaller the delay increment between each skewed clock signal. For example, at a clock frequency of 500 MHz, the minimum delay between the outputs will be two nanoseconds. The delay increment will be precise because the clock is locked to an external phase-locked loop. However, Gazelle only provides TTL compatible outputs. Further, Gazelle utilizes gallium arsenide technology to implement the internal circuitry that operates at high frequencies and generate the internal clock signal. This concept can not be applied to provide CMOS output levels because in order to achieve precise delays as small as two nanoseconds, CMOS circuits would have to run at 500 MHz. Such a circuit would be impractical and difficult to manufacture.
Hence, a need exists for a circuit that provides CMOS level phase shifted clock output signals with respect to an input data signal.